The present invention relates generally to the clock generation in a switching node of a network such as a Wide Access Network (WAN), and particularly to a clock control device used in such a node for obtaining non-disruptive backup clock switching when the master clock fails.
A WAN is composed of nodes connected by lines which may carry a clock originating from a source clock, also called reference clock, and having various characteristics, such as rate and quality (including jitter, short term and long term stability). The clock quality is often referenced to criteria such as the Stratum model which determines several values : Stratum 0, Stratum 1, Stratum 2. . . the first defining the best quality. Thus, primary time standard clocks are Stratum 0. If a clock is continuously synchronized to a Stratum 0 server, the clock is then a Stratum 1,which is generally found on networks such as ISDN networks. In turn a Stratum 2 clock is synchronized to a Stratum 1 and so forth.
The lines connected to a node may have different speed and different quality, and may be not synchronous. Some lines may be without clock with the necessity for the node to provide the clock with the correct frequency and characteristics on this line. Another line may have a common clock for transmit and receive sides (e.g. X.21) or separate clocks (e.g. V.35). In other cases, the node may have use of a transmit clock but need to provide a receive clock.
Although nodes are generally able to generate a clock by using an internal oscillator, such a clock has Stratum level which is lower than the level available on the Public Switched Network (such as PTT) or some public equipment such as a PBX. In other words, the quality of such a clock would not normally allow it to be used as a master clock for the node.
Accordingly, the master clock of is node is normally generated using a high quality clock received on a line. But any such clock may fail. To deal with the possibility of such a failure, the node maintains a list, ordered by priority, of the clocks to be used in the event of unavailability of higher priority clocks. In addition, a node must have a mechanism able to switch from one clock to another one in order to generate all the clocks needed in the node.
What is done generally is the following. First a mechanism is installed on each line to check the presence and quality of the clock. This checking is continuous in order to allow a dynamic backup switching to another clock. Once a clock is selected, another function called the clock module, establishes a Phase Lock Loop (PLL) with respect to the reference. This mechanism is required as the source clocks don""t have the same speed and an intermediate clock having always the same frequency should be phased locked in order to generate all the clocks within the node. So, the phase locked clock, the master clock of the node, is replicated at different rates and distributed to all interfaces requiring clocking.
When a failure occurs, the mechanism which checks the presence and quality of the clock used to generate the master clock informs the control and priority mechanism to switch to the highest priority available clock in the defined list. The clock is then switched in input to the PLL and all the mechanisms re-synchronize on the new clock. Unfortunately, the switching is not immediate. When the switching to the new clock is achieved, significant jitter may be introduced, resulting in data loss in different parts of the node and introducing communication errors during a short period. As the quality of a backup clock is lower than the quality of the previous-used clock, more bit errors may occur until a necessary maintenance operation can be performed where the clock can be switched without any problem.
Accordingly, a main object of the invention is to provide a clock control mechanism able to continuously generate the master clock used in a node without loss of data when the clock currently used to generate the master clock happens to fail.
The invention relates to a clock control device in a switching node of a network connected to other network nodes and to data terminal equipments by a number of connection lines. The node includes an internal low Stratum level reference clock and receives a one or more high Stratum level clocks over one or more of the connection lines. One of these high Stratum level clocks is normally used to generate a Master Clock for the node. The clock control device is used to select a different one of the plurality of high level Stratum clocks when the clock currently used to generate the Master Clock fails. For each high level Stratum clock, the clock control device includes a phase lock circuit for phase locking the reference clock on the selected clock and obtaining a plurality of phase reference clocks. Phase alignment circuits are associated with each of the phase locked reference clocks for continuously aligning its phase on the phase of the Master Clock if this phase locked reference clock is not the one currently used to generate the Master Clock, whereby the Master Clock keeps on being generated without loss of data when the clock currently used to generate the Master Clock happens to fail.